As is known in the art, there are several types of active devices used at microwave and millimeter frequencies to provide amplification of radio frequency signals. In general, one of the more common semiconductor devices used at these frequencies is the high electron mobility transistor (HEMT). Typically, HEMTs are formed from Group III-V materials such as gallium arsenide (GaAs) or indium phosphide (InP). In a HEMT there is a doped donor/undoped spacer layer of one material and an undoped channel layer of a different material. A heterojunction is formed between the doped donor/undoped spacer layer and the undoped channel layer. Due to the conduction band discontinuity at the heterojunction, electrons are injected from the doped donor/undoped spacer layer into the undoped channel layer. Thus, electrons from the large bandgap donor layer are transferred into the narrow bandgap channel layer where they are confined to move only in a plane parallel to the heterojunction. Consequently, there is spatial separation between the donor atoms in the donor layer and the electrons in the channel layer resulting in low impurity scattering and good electron mobility.
One device which has been found to provide good device characteristics such as breakdown voltage, output currents, and pinch-off voltage is a double recessed HEMT. Such a device is fabricated with two aligned recesses in which the gate is formed. The recesses are typically formed by wet etching the device. The etching process is periodically interrupted and the device is tested for certain characteristics, e.g., current. If the characteristics meet the desired criteria, then etching for that recess is terminated. Otherwise, the etching continues. This process continues until both recesses meet the established criteria. This process takes time and money to repeatedly stop the etching and test the device. Also, the etching is not uniform across the wafer, resulting in inconsistent device characteristics across the wafer and low yield of acceptable devices on the wafer.
Presently, there are other major problems impeding the fabrication of double recess High Electron Mobility Transistors (HEMTs). As the technology moves towards smaller dimensions for improved performance, the ability to place a 0.15 micron gate recess pattern within a 0.6 micron first recess pattern is becoming extremely difficult, if not impossible, due to the alignment capability certain electron beam lithography tools. If a tool has an alignment accuracy of 0.15 micrometers, then the overlay accuracy of two layers (first recess pattern and gate pattern) on top of one another is square root of (0.152+0.152)=0.21 micrometers. Another e-beam lithography system has a better overlay accuracy of square root of (0.12+0.12)=0.14 micrometers. These misalignments of a 0.15 micrometer gate recess pattern within the 0.6 micrometer first recess, often result in placement of the edge of the gate within 0.015-0.085 micrometer of the highly doped cap layer defined by the first recess. This results in very low device and circuit yields due to shorting. One solution would be to use extremely expensive optical steppers, which could place the gate pattern with a maximum misalignment of 0.04 microns. Secondly, the cost of 2 separate electron-beam writes (first recess and gate) results in a costly product, since these are the most expensive and time consuming steps of the entire process. Finally, the current gate etch technology is non-selective. The devices are gate etched and re-etched repeatedly until a desired current is met, resulting in non-uniformities across the wafer.
A single-beam write process is described in an article by Grundbacher et al, published in IEEE Electron Devices, Vol. 44, No. 12, December 1997, pg. 2136-2142. This process provides two recesses with a single-beam write. However, the process uses a four-layer polymethylmethacrylate (PMMA) resist process with electron-beam written with two patterns on top of each other (i.e., the first recess and gate). The process would be very difficult to reproduce across a four-inch wafer and would require a relatively long writing time in order to pattern the wide first recess dimension. First the process requires a high density, low bias etcher (ECR, TCP, ICP) to minimize the damage to the Schottky layer by the accelerated ions used in the etching process. Secondly, the process has the disadvantage in that there must be concern of the erosion of the thin layers of PMMA used in their resist structure from ion bombardment. Finally, liftoff of the PMMA (and therefore the gate metal on the resist) is relatively difficult after it has been hardened in the high temperature plasma.
Other processes are described in U.S. Pat. Nos. 4,616,400, 5,364,816, and 5,556,797 all of which describe processes where a single or multiples layers of resist are patterned a first wet or dry chemical etch is used. The resist layer(s) is then “pulled back” via non-directional plasma etching or redeveloping of the resist to increase it's original dimension. A second etch is then required.